Transceiver Interface Bit Ordering (core_mode 0x0, 0x1, 0x2) - 1.1 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2022-07-21
Version
1.1 English

When operating in ILKN mode (with or without FEC) and the ctl_core_mode[1:0] field of the CFG_CORE_MODE_REG register is set to 0x1 or 0x2, the bit ordering for all lanes is as described in the following tables.

Table 1. TX ILKN Bit Ordering Summary (core_mode = 0x1, 0x2)
ILKN Lane ILKN Lane for Stats ILKN Output core_mode 1 = 0x1 intf_mode 2 = 0x0 gearbox_mode 3 = 0x0 ILKN Output core_mode 1 = 0x2 intf_mode 2 = 0x0 gearbox_mode 3 = 0x0 ILKN Output core_mode 1 = 0x2 intf_mode 2 = 0x1 gearbox_mode 3 = 0x0
0 0 tx_serdes_data0[39:0] tx_serdes_data0[39:0] tx_serdes_data0[79:0]
1 1 tx_serdes_data1[39:0] tx_serdes_data1[39:0] tx_serdes_data1[79:0]
2 2 tx_serdes_data2[39:0] tx_serdes_data2[39:0] tx_serdes_data2[79:0]
3 3 tx_serdes_data3[39:0] tx_serdes_data3[39:0] tx_serdes_data3[79:0]
4 4 tx_serdes_data4[39:0] tx_serdes_data4[39:0] tx_serdes_data4[79:0]
5 5 tx_serdes_data5[39:0] tx_serdes_data5[39:0] tx_serdes_data5[79:0]
6 6 tx_serdes_data6[39:0] tx_serdes_data6[39:0] tx_serdes_data6[79:0]
7 7 tx_serdes_data7[39:0] tx_serdes_data7[39:0] tx_serdes_data7[79:0]
8 8 tx_serdes_data8[39:0] tx_serdes_data8[39:0] tx_serdes_data8[79:0]
9 9 tx_serdes_data9[39:0] tx_serdes_data9[39:0] tx_serdes_data9[79:0]
10 10 tx_serdes_data10[39:0] tx_serdes_data10[39:0] tx_serdes_data10[79:0]
11 11 tx_serdes_data11[39:0] tx_serdes_data11[39:0] tx_serdes_data11[79:0]
12 12 tx_serdes_data12[39:0] tx_serdes_data12[39:0] tx_serdes_data12[79:0]
13 13 tx_serdes_data13[39:0] tx_serdes_data13[39:0] tx_serdes_data13[79:0]
14 14 tx_serdes_data14[39:0] tx_serdes_data14[39:0] tx_serdes_data14[79:0]
15 15 tx_serdes_data15[39:0] tx_serdes_data15[39:0] tx_serdes_data15[79:0]
16 16 tx_serdes_data16[39:0] tx_serdes_data16[39:0] tx_serdes_data16[79:0]
17 17 tx_serdes_data17[39:0] tx_serdes_data17[39:0] tx_serdes_data17[79:0]
18 18 tx_serdes_data18[39:0] tx_serdes_data18[39:0] tx_serdes_data18[79:0]
19 19 tx_serdes_data19[39:0] tx_serdes_data19[39:0] tx_serdes_data19[79:0]
20 20 tx_serdes_data20[39:0] tx_serdes_data20[39:0] tx_serdes_data20[79:0]
21 21 tx_serdes_data21[39:0] tx_serdes_data21[39:0] tx_serdes_data21[79:0]
22 22 tx_serdes_data22[39:0] tx_serdes_data22[39:0] tx_serdes_data22[79:0]
23 23 tx_serdes_data23[39:0] tx_serdes_data23[39:0] tx_serdes_data23[79:0]
  1. core_mode refers to ctl_core_mode[1:0].
  2. intf_mode refers to c0_ctl_tx_serdes_intf_mode[1:0].
  3. gearbox_mode refers to c0_ctl_tx_gearbox_mode[1:0].
Table 2. RX ILKN Bit Ordering Summary (core_mode = 0x1, 0x2)
ILKN Lane ILKN Lane for Stats ILKN Output core_mode 1 = 0x1 intf_mode 2 = 0x0 gearbox_mode 3 = 0x0 ILKN Output core_mode 1 = 0x2 intf_mode 2 = 0x0 gearbox_mode 3 = 0x0 ILKN Output core_mode 1 = 0x2 intf_mode 2 = 0x1 gearbox_mode 3 = 0x0
0 0 rx_serdes_data0[39:0] rx_serdes_data0[39:0] rx_serdes_data0[79:0]
1 1 rx_serdes_data1[39:0] rx_serdes_data1[39:0] rx_serdes_data1[79:0]
2 2 rx_serdes_data2[39:0] rx_serdes_data2[39:0] rx_serdes_data2[79:0]
3 3 rx_serdes_data3[39:0] rx_serdes_data3[39:0] rx_serdes_data3[79:0]
4 4 rx_serdes_data4[39:0] rx_serdes_data4[39:0] rx_serdes_data4[79:0]
5 5 rx_serdes_data5[39:0] rx_serdes_data5[39:0] rx_serdes_data5[79:0]
6 6 rx_serdes_data6[39:0] rx_serdes_data6[39:0] rx_serdes_data6[79:0]
7 7 rx_serdes_data7[39:0] rx_serdes_data7[39:0] rx_serdes_data7[79:0]
8 8 rx_serdes_data8[39:0] rx_serdes_data8[39:0] rx_serdes_data8[79:0]
9 9 rx_serdes_data9[39:0] rx_serdes_data9[39:0] rx_serdes_data9[79:0]
10 10 rx_serdes_data10[39:0] rx_serdes_data10[39:0] rx_serdes_data10[79:0]
11 11 rx_serdes_data11[39:0] rx_serdes_data11[39:0] rx_serdes_data11[79:0]
12 12 rx_serdes_data12[39:0] rx_serdes_data12[39:0] rx_serdes_data12[79:0]
13 13 rx_serdes_data13[39:0] rx_serdes_data13[39:0] rx_serdes_data13[79:0]
14 14 rx_serdes_data14[39:0] rx_serdes_data14[39:0] rx_serdes_data14[79:0]
15 15 rx_serdes_data15[39:0] rx_serdes_data15[39:0] rx_serdes_data15[79:0]
16 16 rx_serdes_data16[39:0] rx_serdes_data16[39:0] rx_serdes_data16[79:0]
17 17 rx_serdes_data17[39:0] rx_serdes_data17[39:0] rx_serdes_data17[79:0]
18 18 rx_serdes_data18[39:0] rx_serdes_data18[39:0] rx_serdes_data18[79:0]
19 19 rx_serdes_data19[39:0] rx_serdes_data19[39:0] rx_serdes_data19[79:0]
20 20 rx_serdes_data20[39:0] rx_serdes_data20[39:0] rx_serdes_data20[79:0]
21 21 rx_serdes_data21[39:0] rx_serdes_data21[39:0] rx_serdes_data21[79:0]
22 22 rx_serdes_data22[39:0] rx_serdes_data22[39:0] rx_serdes_data22[79:0]
23 23 rx_serdes_data23[39:0] rx_serdes_data23[39:0] rx_serdes_data23[79:0]
  1. core_mode refers to ctl_core_mode[1:0].
  2. intf_mode refers to c0_ctl_rx_serdes_intf_mode[1:0].
  3. gearbox_mode refers to c0_ctl_rx_gearbox_mode[1:0].