There are three clock domains in the DPUCVDX8G IP:
s_axi_aclkfor register configuration.
m_axi_aclkfor general logic control in the DPUCVDX8G PL component.
s00_aie_aclkfor the AI Engine component.
The two input clocks on the PL component can each be configured at different
frequencies independently. Generally, the
s_axi_aclk is set at a
lower frequency to obtain a better timing closure. Therefore, the corresponding reset for the two
input clocks must be configured correctly.
s00_aie_aclk is the output clock of the AI
Engine module. This clock is output to the NoC for data transmission between the AI Engine and
the NoC. The frequency of
s00_aie_aclk can be set in the
The following figure shows the three clock domains.
s_axi_aclkis used for the register configuration module. This module receives the DPUCVDX8G configuration though the S_AXI_CONTROL interface. The DPU configuration registers are updated at a very low frequency and most of those registers are set at the start of a task. It is recommended to use a frequency of 100 MHz for the S-AXI clock.
m_axi_aclkis used for most of the logic in the PL component except for the register configuration module. The
m_axi_aclkis also used for the data transmission between the DPUCVDX8G PL and the NoC. The
m_axi_aclkis the associated clock for all the AXI4 master interface and AXI4-Stream interface from the PL component. The recommended frequency for this clock is 333 MHz.
s00_aie_aclk(connected with the pin
s00_axi_aclkof AIE IP) is the working clock for the AI Engine array, and interface between NOC. Its frequency is set by AIE_CORE_REF_CTRL_FREQMHZ in the AIE IP, and should set as four times of the frequency of
m_axi_aclk(connected with the pin
aclk0of AIE IP), or the maximum AIE frequency (for example, 1.25GHz for XCV1902-2MP part on the VCK190 board). The frequency of AIE_CORE_REF_CTRL_FREQMHZ can be set in the
postlink.tclfile in the Vitis flow.