This section briefly describes the DPU-V1 (formerly known as xfDNN) front-end compilers. Here, a Caffe and TensorFlow interfaces are presented, both of which are built on top of a common intermediate representation. These interfaces are common to all DPUs.
This section also describes the procedure that is used in combination with examples (refer to software distribution), model quantization, and the proceeding sub-graph. As today, the compilers comes as open source and it provides further insights.
Only the necessary steps and some of the context are presented here to give familiarity with this new environment. It is assumed that your environment is set up and running, and that you are considering a network (such as a classification network) and want to see the instructions for generating it to run on a DPU-V1 design.
If the final goal is to inspect FPGA codes and to infer a time estimate, the compiler can be used in isolation. If the final goal is to execute the network on an FPGA instance, the DPU-V1 compiler must be used in combination of a partitioner. There are two tools for this purpose in the following chapters. One is for Caffe and the other is for Tensorflow. For Caffe, the partitioner can directly use the compiler outputs and feed the run time. This is because the partitioner just broke the computation in a single FPGA subgraph. The Tensor Flow partitioner will allow multiple subgraphs. Refer to the following chapter for more details.