The DPU-v2 IP has been optimized for Xilinx MPSoC devices. This IP can be integrated as a block in the programmable logic (PL) of the selected Zynq-7000 SoC and Zynq UltraScale+ MPSoCs with direct connections to the processing system (PS). The configurable version DPU IP is released together with Vitis AI. DPU is user-configurable and exposes several parameters which can be specified to optimize PL resources or customize the enabled features. For more information, see the Zynq DPU v3.1 IP Product Guide (PG338).
Figure 1. DPU-V2 Architecture
