The compiler optimizations can be modified by passing the applicable compiler arguments either through positional argument or options arguments to the Partitioner class TFxdnnRT.
If model is not properly frozen, the compiler might fail optimizing some operations such as batchnorm.
startnode and finalnode sets should be a vertex separators. Meaning, removal of startnode or finalnode should separate the graph into two distinct connected components (except when startnode is a subset of graph placeholders).
Wherever possible, do not specify cut nodes between layers that are executed as a single macro layers, e.g., for Conv(x) -> BiasAdd(x), placing Conv(x) in a different FPGA partition than BiasAdd(x) may result in suboptimal performance (throughput, latency, and accuracy).
The partitioner initialization requires quant_cfgfile to exist to be able to create
executable code for FPGA. In case FPGA execution is not intended, this requirement can
be circumvented by setting