The AXI4-Lite interface has its own clock and reset. The AXI4-Lite clock (
s_axi_aclk) is independent of the
remainder of the ILKNF clocks and can be any frequency
to a maximum of 300 MHz.
s_axi_aresetpin results in the following:
- A reset of the AXI4-Lite port and ILKNF APB3 control logic, stopping any in-flight writes or reads.
- A reset of the soft reset registers found in CFG_C0_RESET_REG, CFG_TX_SERDES_RESET_REG and CFG_RX_SERDES_RESET_REG.
An AXI4-Lite reset does not reset the internal configuration registers.