The ILKNF IP contains a soft logic 32-bit AXI4-Lite interface block to allow access to the APB3 interface of the integrated IP. Through the AXI4-Lite interface, you can access the internal configuration registers. For more details on the AXI4-Lite interface, see the AXI to APB Bridge LogiCORE IP Product Guide (PG073).
|s_axi_aclk||I||This clock is used for both the AXI4-Lite bridge soft logic and the ILKNF APB3 port
Note: The s_axi_clk must be present for the ILKNF to function. If this clock is interrupted, the ILKNF IP enters an error state.
|s_axi_areset||I||Active-High reset for the AXI4-Lite port. Asserting this reset alters the port control logic and stops any in-flight writes or reads. It does not reset the internal configuration registers, with exceptions listed below. ||
A complete description of the register map and the individual registers can be found in the Register Space section.