Features - 1.2 English

Versal ACAP Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2023-01-19
Version
1.2 English
  • Up to six lanes of 112 Gb/s
  • Single-core up to 1 x 600 Gb/s
    • Up to 12 lanes of 56.42 Gb/s
    • Up to 24 lanes of 28.21 Gb/s
  • Supports a wide range of transceiver rates, with an optimized architecture for the following rates:
    • 12.5 Gb/s, 25.78125 Gb/s, 28.21 Gb/s, 53.125 Gb/s, 56.42 Gb/s, 106.25 Gb/s, 112 Gb/s
  • 40-bit, 80-bit, or 160-bit interface to the serial transceiver
  • Supports multiple AXI4-Stream user interface widths:
    • 2048 bits, 1536 bits, 1024 bits, 768 bits, 512 bits
  • Optional RS-FEC for up to 12 Interlaken lanes of 56.42 Gb/s
  • FEC-only mode supporting:
    • Up to 6 instances of 112 Gb/s RS-FEC encoding and decoding functions
    • Up to 12 instances of 56.42 Gb/s RS-FEC encoding and decoding functions