The synchronous RX interface provides packet-oriented data much like the TX AXI4-Stream interface accepts. All signals are synchronous with the
rising-edge of the
c0_axi_clk clock. The following figure shows a
sample waveform for two data transactions for 65-byte packets using a 512-bit segmented
Similar to the TX AXI4-Stream interface, the RX AXI4-Stream interface is divided into 128-bit segments, with multiple
transfers presented in parallel during the same clock cycle. The number of segments is
based on the width of the bus as programmed in the
c0_ctl_rx_axis_width[2:0] field of the CFG_C0_RX_OVERALL_REG
register. The first of the 128-bit transfers occurs on segment 0 (that is,
rx_axis_tdata0), the second on segment 1 (that is,
rx_axis_tdata1), and so forth.
Data is supplied on segment <M> by the ILKNF subsystem on every
c0_axi_clk clock cycle when
rx_axis_tuser_ena<M> is asserted. This signal qualifies the other
outputs of segment <M> of the RX AXI4-Stream
interface. The RX core logic stores incoming data and does not forward it until it has a
sufficient quantity. Consequently, there can be clock cycles where none of the
rx_axis_tuser_ena<M> signals are asserted.
In any cycle where any
rx_axis_tuser_ena<M> is asserted,
rx_axis_tuser_ena0 is also required to be asserted. Furthermore, segments
are filled in sequence with no gaps between active segments. For example, if
rx_axis_tuser_ena<i> is set to 1, then
rx_axis_tuser_ena<i - 1> is also set to 1, for i
- 1 to 15 for a 2048-bit bus
- 1 to 11 for a 1536-bit bus
- 1 to 7 for a 1024-bit bus
- 1 to 3 for a 512-bit bus
The RX is similar to the TX, in that
rx_axis_tuser_sop<M> identifies the start of a packet on segment
rx_axis_tuser_eop<M> identifies the
end of a packet on segment <M>. Both
rx_axis_tuser_eop<M> are asserted during the same cycle for packets
that are less than or equal to the segment width.
As in the TX, the first byte of a packet that starts on segment <M> is
supplied on bits [127:120] of
second byte on bits [119:112], and so forth.
Portions of packets are written on the bus segments in the full width of the
segment (16 bytes) unless for the last segment of the packet. When
rx_axis_tuser_eop<M> is asserted on segment <M>,
rx_axis_tuser_mty<M> bus indicates how many byte
lanes in the segment are invalid. The encoding is the same as for
During the last cycle of a packet, when
rx_axis_tuser_eop<M> is asserted with
rx_axis_tuser_err<M> can also be asserted to indicate an error in the
packet ended on segment<M>.
There is no mechanism to backpressure the RX AXI4-Stream interface. The user logic must be capable of receiving data
rx_axis_tuser_ena<M> is asserted. The
Interlaken flow control mechanism can be used to stop the flow of data, either using the
in-band or out of band protocol, or both.
The data provided by the RX AXI4-Stream
interface is in the same sequence as it is received from the Interlaken bus. Packets can
be interleaved and are distinguished using the channel number presented on
The RX segmented AXI4-Stream bus can contain more than one SOP and more than one EOP. There is no requirement to accommodate Burst Control Words on the receive side AXI4-Stream interface (they have already been processed) and therefore packets can be packed as efficiently as possible when they arrive.