The bus has a total number of segments calculated by dividing the width of
the bus (set by the value of the
c0_ctl_tx_axis_width[2:0] register field of the CFG_C0_TX_OVERALL_REG
register and the
field of the CFG_C0_RX_OVERALL_REG register) by 128 (the size of a segment).
The 128-bit segments are ordered 0 to 15 in the case of a 2048-bit
AXI4-Stream bus. The first of the 128-bit
transfers occurs on segment 0, the second on segment 1, and so forth. During each
c0_axi_clk clock cycle that data is transferred on
the segmented AXI4-Stream bus, segment 0 must be
active. The segmented bus is aligned such that the first bit of the incoming data is
placed at the MSB of segment 0.