Simulation might take a long time due to core alignment, FEC alignment, and the segment buffer initialization process of the packet generator. A SIM_SPEED_UP directive is available to improve the simulation time by reducing the TX and RX Interlaken FEC frame length (in configurations using FEC) and initializing only eight entries of each segment buffer of the packet generator.
The test bench writes to all RAM cells in all segments to initialize the packet scheduling data because the same process is followed on hardware. However, this is time-consuming during simulation. In order to cut down on the time taken to initialize the RAM cells through the AXI4-Lite bus, the test bench provides an alternative method to force-initialize the memory at the beginning of the simulation. This procedure can be enabled by setting the test bench parameter force_ram_init to 1.