DPUCVDX8G Configurable Registers - 1.2 English

DPUCVDX8G for Versal ACAPs Product Guide (PG389)

Document ID
PG389
Release Date
2022-06-24
Version
1.2 English

The DPUCVDX8G configurable registers are used for configuring Xilinx IPs.

The reg_dpu_instr_addr register is used to indicate the instruction address of the DPUCVDX8G. The instruction address is a 44-bit signal consist of the 32-bit of INSTR_ADDR_L and lower 12-bit of INSTR_ADDR_H. The lower 12-bit of reg_dpu_instr_addr are set to zero in the DPUCVDX8G logic. Hence, the available instruction address for the DPUCVDX8G ranges from 0x1000 to 0xFFF_FFFF_F000.

The reg_dpu_base_addr register is used to indicate the address of input image and parameters in external memory. The width of the DPUCVDX8G base address is 44-bits, so it can support address ranges from 0 to 16 TB. All registers are 32-bits wide, so two registers are required to compose the 44-bit wide base address. Reg BATCH0_ADDR0_L represents the lower 32-bits of base address0 of the DPUCVDX8G batch handler0 and BATCH0_ADDR0_H represents the upper 12-bits of base address0. For each DPUCVDX8G batch handler, there are eight base addresses. The DPUCVDX8G supports up to six batch handlers, so there are six groups of batch base addresses.

The description of those registers are shown in the following table.

Table 1. DPUCVDX8G Configurable Registers
Name Offset Address Bits Type Description
IRQ_CLR 0x40 [31:1]   Reserved
    [0] r/w When asserted, the DPUCVDX8G interrupt is cleared. The IRQ_CLR will be cleared after the interrupt is cleared.
INSTR_ADDR_L 0x50 [31:0] r/w The lower 32-bit of start address for fetching instructions from an external memory.
INSTR_ADDR_H 0x54 [31:12]   Reserved
[11:0] r/w The higher 12-bit of start address for fetching instructions from an external memory.
BATCH0_ADDR0_L 0x200 [31:0] r/w The lower 32-bit base address0 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR0_H 0x204 [11:0] r/w The higher 12-bit base address0 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR1_L 0x208 [31:0] r/w The lower 32-bit base address1 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR1_H 0x20c [11:0] r/w The higher 12-bit base address1 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR2_L 0x210 [31:0] r/w The lower 32-bit base address2 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR2_H 0x214 [11:0] r/w The higher 12-bit base address2 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR3_L 0x218 [31:0] r/w The lower 32-bit base address3 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR3_H 0x21c [11:0] r/w The higher 12-bit base address3 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR4_L 0x220 [31:0] r/w The lower 32-bit base address4 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR4_H 0x224 [11:0] r/w The higher 12-bit base address4 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR5_L 0x228 [31:0] r/w The lower 32-bit base address5 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR5_H 0x22c [11:0] r/w The higher 12-bit base address5 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR6_L 0x230 [31:0] r/w The lower 32-bit base address6 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR6_H 0x234 [11:0] r/w The higher 12-bit base address6 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR7_L 0x238 [31:0] r/w The lower 32-bit base address7 of batch handler0 for loading and saving image and weights.
BATCH0_ADDR7_H 0x23c [11:0] r/w The higher 12-bit base address7 of batch handler0 for loading and saving image and weights.
BATCH1_ADDR0_L 0x240 [31:0] r/w The lower 32-bit base address0 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR0_H 0x244 [11:0] r/w The higher 12-bit base address0 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR1_L 0x248 [31:0] r/w The lower 32-bit base address1 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR1_H 0x24c [11:0] r/w The higher 12-bit base address1 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR2_L 0x240 [31:0] r/w The lower 32-bit base address2 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR2_H 0x244 [11:0] r/w The higher 12-bit base address2 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR3_L 0x248 [31:0] r/w The lower 32-bit base address3 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR3_H 0x24c [11:0] r/w The higher 12-bit base address3 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR4_L 0x250 [31:0] r/w The lower 32-bit base address4 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR4_H 0x254 [11:0] r/w The higher 12-bit base address4 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR5_L 0x268 [31:0] r/w The lower 32-bit base address5 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR5_H 0x26c [11:0] r/w The higher 12-bit base address5 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR6_L 0x270 [31:0] r/w The lower 32-bit base address6 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR6_H 0x274 [11:0] r/w The higher 12-bit base address6 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR7_L 0x278 [31:0] r/w The lower 32-bit base address7 of batch handler1 for loading and saving image and weights.
BATCH1_ADDR7_H 0x27c [11:0] r/w The higher 12-bit base address7 of batch handler1 for loading and saving image and weights.
BATCH2_ADDR0_L 0x280 [31:0] r/w The lower 32-bit base address0 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR0_H 0x284 [11:0] r/w The higher 12-bit base address0 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR1_L 0x288 [31:0] r/w The lower 32-bit base address1 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR1_H 0x28c [11:0] r/w The higher 12-bit base address1 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR2_L 0x290 [31:0] r/w The lower 32-bit base address2 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR2_H 0x294 [11:0] r/w The higher 12-bit base address2 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR3_L 0x298 [31:0] r/w The lower 32-bit base address3 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR3_H 0x29c [11:0] r/w The higher 12-bit base address3 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR4_L 0x2a0 [31:0] r/w The lower 32-bit base address4 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR4_H 0x2a4 [11:0] r/w The higher 12-bit base address4 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR5_L 0x2a8 [31:0] r/w The lower 32-bit base address5 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR5_H 0x2ac [11:0] r/w The higher 12-bit base address5 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR6_L 0x2b0 [31:0] r/w The lower 32-bit base address6 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR6_H 0x2b4 [11:0] r/w The higher 12-bit base address6 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR7_L 0x2b8 [31:0] r/w The lower 32-bit base address7 of batch handler2 for loading and saving image and weights.
BATCH2_ADDR7_H 0x2bc [11:0] r/w The higher 12-bit base address7 of batch handler2 for loading and saving image and weights.
BATCH3_ADDR0_L 0x2c0 [31:0] r/w The lower 32-bit base address0 of batch handler0 for loading and saving image and weights.
BATCH3_ADDR0_H 0x2c4 [11:0] r/w The higher 12-bit base address0 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR1_L 0x2c8 [31:0] r/w The lower 32-bit base address1 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR1_H 0x2cc [11:0] r/w The higher 12-bit base address1 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR2_L 0x2d0 [31:0] r/w The lower 32-bit base address2 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR2_H 0x2d4 [11:0] r/w The higher 12-bit base address2 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR3_L 0x2d8 [31:0] r/w The lower 32-bit base address3 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR3_H 0x2dc [11:0] r/w The higher 12-bit base address3 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR4_L 0x2e0 [31:0] r/w The lower 32-bit base address4 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR4_H 0x2e4 [11:0] r/w The higher 12-bit base address4 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR5_L 0x2e8 [31:0] r/w The lower 32-bit base address5 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR5_H 0x2ec [11:0] r/w The higher 12-bit base address5 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR6_L 0x2f0 [31:0] r/w The lower 32-bit base address6 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR6_H 0x2f4 [11:0] r/w The higher 12-bit base address6 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR7_L 0x2f8 [31:0] r/w The lower 32-bit base address7 of batch handler3 for loading and saving image and weights.
BATCH3_ADDR7_H 0x2fc [11:0] r/w The higher 12-bit base address7 of batch handler3 for loading and saving image and weights.
BATCH4_ADDR0_L 0x300 [31:0] r/w The lower 32-bit base address0 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR0_H 0x304 [11:0] r/w The higher 12-bit base address0 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR1_L 0x308 [31:0] r/w The lower 32-bit base address1 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR1_H 0x30c [11:0] r/w The higher 12-bit base address1 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR2_L 0x310 [31:0] r/w The lower 32-bit base address2 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR2_H 0x314 [11:0] r/w The higher 12-bit base address2 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR3_L 0x318 [31:0] r/w The lower 32-bit base address3 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR3_H 0x31c [11:0] r/w The higher 12-bit base address3 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR4_L 0x320 [31:0] r/w The lower 32-bit base address4 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR4_H 0x324 [11:0] r/w The higher 12-bit base address4 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR5_L 0x328 [31:0] r/w The lower 32-bit base address5 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR5_H 0x32c [11:0] r/w The higher 12-bit base address5 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR6_L 0x330 [31:0] r/w The lower 32-bit base address6 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR6_H 0x334 [11:0] r/w The higher 12-bit base address6 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR7_L 0x338 [31:0] r/w The lower 32-bit base address7 of batch handler4 for loading and saving image and weights.
BATCH4_ADDR7_H 0x33c [11:0] r/w The higher 12-bit base address7 of batch handler4 for loading and saving image and weights.
BATCH5_ADDR0_L 0x340 [31:0] r/w The lower 32-bit base address0 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR0_H 0x344 [11:0] r/w The higher 12-bit base address0 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR1_L 0x348 [31:0] r/w The lower 32-bit base address1 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR1_H 0x34c [11:0] r/w The higher 12-bit base address1 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR2_L 0x350 [31:0] r/w The lower 32-bit base address2 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR2_H 0x354 [11:0] r/w The higher 12-bit base address2 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR3_L 0x358 [31:0] r/w The lower 32-bit base address3 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR3_H 0x35c [11:0] r/w The higher 12-bit base address3 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR4_L 0x360 [31:0] r/w The lower 32-bit base address4 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR4_H 0x364 [11:0] r/w The higher 12-bit base address4 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR5_L 0x368 [31:0] r/w The lower 32-bit base address5 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR5_H 0x36c [11:0] r/w The higher 12-bit base address5 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR6_L 0x370 [31:0] r/w The lower 32-bit base address6 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR6_H 0x374 [11:0] r/w The higher 12-bit base address6 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR7_L 0x378 [31:0] r/w The lower 32-bit base address7 of batch handler5 for loading and saving image and weights.
BATCH5_ADDR7_H 0x37c [11:0] r/w The higher 12-bit base address7 of batch handler5 for loading and saving image and weights.