The DPUCVDX8G has the following features:
- One AXI4-Lite slave interface for accessing configuration and status registers.
- One AXI4 master interface for DPU instruction fetch.
- DPU with 32 AI Engine support batch sizes 1-6.
- DPU with 64 AI Engine support batch sizes 1-5.
- Supports a maximum of three homogeneous compute units (CU).
- Supports a configurable number of AXI4 interfaces for activation and feature map load/store.
The following list highlights key supported operators for the DPUCVDX8G:
- Convolution and transposed convolution, 2D and 3D
- Depthwise convolution and depthwise transposed convolution, 2D and 3D
- Max pooling
- Average pooling
- ReLU, ReLU6, Leaky ReLU, Hard Sigmoid, and Hard Swish
- Elementwise-Sum and Elementwise-Multiply, 2D and 3D
- Dilation
- Reorg
- Fully connected layer
- Concat, Batch Normalization