The following table lists the clocks that are present in the MRMAC. Note that all datapath-related clocks are per-port. Although in certain operating modes, clocks are tied together internally and the lower-numbered port clock is used.
|AXI4-Lite||s_axi_clk||AXI4-Lite processor interface clock.|
|AXI4-Stream interface clocks. These clocks are used by the AXI4-Stream interface when in independent clock mode. They are also used by certain timestamping signals as well as a number of device statistics and flow control signals. The clocks are shared between two ports of the MRMAC. The tx_axi_clk and rx_axi_clk are shared between Ports 0 and 1, The tx_axi_clk and rx_axi_clk are shared between Ports 2 and 3.|
|Per-port high-speed clocks which drive the MRMAC internals.|
|Per-port high-speed clocks for the GT interface.|
|Per-port clocks for the timestamp interface.|
|Per-port Flex I/F clocks.|
|Per-port Alternate low-frequency clock for the GT interface.|