Example Design Hierarchy - 1.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

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1.3 English

The following figure shows the MRMAC example design. In the block design, the MRMAC and GT Quad Base IP are connected along with the BUFG_GTs. For more information on the GT Quad Base IP, see the Versal ACAP Transceivers Wizard v1.0 LogiCORE IP Product Guide (PG331).

Figure 1. MRMAC Example Design (Simulation)

Figure 2. MRMAC Example Design (Implementation)

Note: The MRMAC Tile section in device is currently done by MRMAC GUI ( default set to "X0Y3"). A sample constraint for MRMAC location "X0Y3" is applied to core.xdc (mrmac_0.xdc) file. A suitable GT also suggested in exdes.xdc (mrmac_0_example_top.xdc) file to lock appropriate GT for the selected MRMAC. If you change these locations, you need to take care of the clocking region and routing feasibly.