The following shows timing diagram examples for the timer adjustments.
System Timer Overwrite
To overwrite the system timer, assert
ctl_tx/rx_ptp_st_overwrite_N and drive the desired 54-bit value onto
the input signal
overwrite is triggered by toggling the signal
ctl_tx/rx_ptp_st_sync_Nsignals come from a clock domain that is asynchronous to the timer's clock domain, hence some small delays for retiming.
As mentioned earlier, if the
ctl_tx/rx_ptp_st_sync_N transition is sampled to the falling edge of
the timer’s clock, a DDR phase compensator automatically adds half a clock period
timer_increment / 2) to the system timer
to help improve timer resolution.
Timer Frequency Set Coarse Adjustment
In this example, the
frequency is set by providing a coarse adjustment to the
ctl_ptp_st_adjustvalue is interpreted as being in units of 2-8 ns, which means it is mapped into the coarse portion of the
increment_value. The sub-nanosecond portion of the
increment_valueis set to
32’d0. To adjust the sub-nanosecond portion of the increment value, use the Timer Frequency Adjust method.
Timer Frequency Adjust Fine Adjustment
Here is an example of fine-tuning the
system_timer frequency by adjusting the sub-nanosecond portion of the
increment value (Method 3 on the Adjustment interface). The adjustment is specified
to be in units of 2-40 ns. The provided signed adjustment
value is added to the existing
used moving forward.
In this example, a signed adjustment value of
32’hBA9D_1F60 is provided. Because this adjustment value is negative,
it results in a subtraction of
reducing the increment value from
In this diagram, a phase shift to the timer value is shown (Method 1 using the Adjustment interface).
increment_valueonly changes for one
system_timeriteration (it is a one-shot adjustment) then returns to its previous value. The maximum allowable adjustment is
18’h3_FFFFin units of 2-8 ns.