GT Quad Transceiver (SerDes) Modes - 1.3 English

The MRMAC is capable of interfacing with the Xilinx® Versal™ GTY transceivers through the programmable logic region. Each GT Quad lane has a dedicated transceiver interface on the MRMAC IP subsystem.

The MRMAC has PCS/PMA lane logic functions including gearbox, scrambling, lane alignment, and lane deskew. For this reason, the transceivers connected to the MRMAC must be configured to operate in RAW mode. The default transceiver lane interface configuration is 16b RAW interface for 10.3125 Gb/s lane logic, 40b RAW interface for 25.78/26.56 Gb/s lane logic, and 80b RAW interface for 53.125 Gb/s lane logic.

For multi-lane PMD lane data rates (such as 100GE or 40GE), the MRMAC GT Quad interface can support per-lane GT Quad recovered clocks in the RX direction. This option reduces transceiver latency and improves 1588 timestamping accuracy at the cost of requiring per-lane FPGA clocking resources.

For designs desiring to reduce the clocking resources consumed by the MRMAC link, the IP also supports having the transceivers configured with per-lane deskew buffering enabled, allowing all RX PMD lanes to share a common master lane clock.

The following table shows a list of all the MRMAC supported interface options for GTY transceivers including the associated line rates, GT datapath width, clock frequency, and the corresponding ctl_serdes_width field setting. The ctl_serdes_width setting is found in the MODE_REG register for each port.