A simple handshaking protocol is used to alert the user logic to the
reception of pause packets using the
For these buses, Bit corresponds to global pause packets and Bits[7:0] correspond to
priority pause packets.
The following steps occur when a pause packet is received:
- If the corresponding bit of
ctl_rx_pause_enable[8:0]is 0, the quanta is ignored and the hard MRMAC stays in step 1. Otherwise, the corresponding bit of the
stat_rx_pause_req[8:0]bus is set to 1 and the received quanta is loaded into a timer.
If one of the bits of
ctl_rx_pause_enable[8:0]is set to 0 (disabled) when the pause processing is in step 2 or later, the subsystem completes the steps as normal until it comes back to step 1.
ctl_rx_check_ackinput is 1, the subsystem waits for you to set the appropriate bit of the
ctl_rx_pause_ack[8:0]bus to 1.
- After you set the proper bit of
ctl_rx_pause_ack[8:0]to 1, or if
ctl_rx_check_ackis 0, the subsystem starts counting down the timer.
- When the timer times out, the subsystem sets
the appropriate bit of
stat_rx_pause_req[8:0]back to 0.
ctl_rx_check_ackinput is 1, the operation is complete when you set the appropriate bit of
ctl_rx_pause_ack[8:0]back to 0.
If you do not set the appropriate bit of
ctl_rx_pause_ack[8:0]back to 0, the core expects the operation complete after 32 clock cycles.
The following is an example of a pause handshaking event.