To allow flexibility in the potential dynamic rate switching of ports, the MRMAC has two AXI4-Stream bus clock inputs to the MRMAC per direction (TX and RX), tx_axi_clk[2,0]
and
rx_axi_clk[2,0]
. The tx_axi_clk[0]
and
rx_axi_clk[0]
pins are used to clock ports 0 and 1. The
tx_axi_clk[2]
and rx_axi_clk[2]
are used to clock ports
2 and 3.
Port | rx_axi_clk and tx_axi_clk Usage for Configured Data Rates | ||||
---|---|---|---|---|---|
10GE | 25GE | 40GE | 50GE | 100GE | |
0 | rx_axi_clk[0], tx_axi_clk[0] | rx_axi_clk[0], tx_axi_clk[0] | rx_axi_clk[0], tx_axi_clk[0] | rx_axi_clk[0], tx_axi_clk[0] | rx_axi_clk[0], tx_axi_clk[0] |
1 | rx_axi_clk[0], tx_axi_clk[0] | rx_axi_clk[0], tx_axi_clk[0] | N/A | N/A | N/A |
2 | rx_axi_clk[2], tx_axi_clk[2] | rx_axi_clk[2], tx_axi_clk[2] | N/A | rx_axi_clk[2], tx_axi_clk[2] | N/A |
3 | rx_axi_clk[2], tx_axi_clk[2] | rx_axi_clk[2], tx_axi_clk[2] | N/A | N/A | N/A |
The MRMAC uses the rx_axi_clk
and tx_axi_clk
to output some latency critical status signals, thus the IP
block requires that the rx_axi_clk
and tx_axi_clk
inputs
be driven by valid clocks regardless of the AXI4-Stream
operating mode. The section for the independent AXI clocking mode describes the acceptable
rx_axi_clk
and tx_axi_clk
.
The AXI4-Stream user interface can be
configured to operate in one of two clocking modes, depending on system latency and
performance requirements. As reflected in Table 1, the desired clock mode is selected using
the ctl_axis_cfg_<N>
field of the port MODE_REG
register.