The AXI4-Stream interface is dynamically re-configurable during run-time to support the selected mode of Ethernet operation. The MRMAC AXI4-Stream interface can be configured as four independent interfaces or ganged together as a wider bus to support the higher data rates. The number of 64-bit data word lanes can be configured to tailor the interface towards low latency performance or low frequency clock rates.
The following table lists the available configuration options. The desired
mode is selected using the control field
ctl_axis_cfg_<N>[2:0] (N = 0... 3) of each MODE_REG register of the port.
The meaning of the various options (segmented versus non-segmented bus structure and low
latency versus independent clock modes) are explained in the following table.
|Selected Data Rate||Selected AXI Clock Mode||AXI Clock Frequency (MHz)||AXI4-Stream Data Width (Bits)||AXI4-Stream Segment Mode||MODE Configuration (ctl_axis_cfg_<N>)|
|100GE||Low Latency||Same as tx_core_clk/ rx_core_clk (for example, 644.531)||256||Non-Segmented||3'b000|
|40GE/50GE||Low Latency||Same as tx_core_clk/ rx_core_clk (for example, 644.531)||128||Non-Segmented||3'b000|
|25GE||Low Latency||Same as tx_core_clk/ rx_serdes_clk (for example, 644.531)||64||Non-Segmented||3'b000|
|10GE||Low Latency||tx_core_clk, rx_serdes_clk (for example, 644.531)||32||Non-Segmented||3'b000|