RSFEC Compensation ROM - 1.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

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1.3 English

Additional timestamp compensation can be obtained when RSFEC is active by enabling the RSFEC Compensation ROM. The user logic might want to enable this feature if it requires that transcoder compression and parity insertion effects be included in the produced timestamp. This compensation is optional and is enabled using the ctl_tx_ptp_rsfec_comp_en field of the CONFIGURATION_1588_REG register. Enabling the compensation ROM is similar to moving the timestamp timing plane to the point where data is RSFEC encoded. Typically this would not be required.

The compensation ROM contains a table of pre-calculated adjustment factors which adjust the timestamp to compensate for the effects of transcoder compression and RSFEC parity bits insertion.

When enabled, the compensation is performed automatically in the egress direction, which is particularly useful when 1-step timestamp insertion is active. In the ingress (receive) direction, you must perform your own RSFEC compensation as the ROM is only available in the egress (transmit) direction. To accomplish this, the user logic can generate its own compensation look-up table. The input to the table is the codeword offset (D_ptp_rsfec_offset_out_N) produced by the receive timestamp interface. The output from the table is described by the following pseudo code:


for (cw_offset=0;cw_offset<80;i++) begin
 adj_val[cw_offset] = round((256*(1-257/264)*cw_offset*64/25)); # (Nominal KR4 block period)


for (cw_offset=0;cw_offset<80;i++) begin
 adj_val[cw_offset] = round((256*(1-257/272)*cw_offset*64/25)); # (Nominal - KP4 block period)

The tables generated by the pseudo code reflect a nominal clock with a standard KR4/KP4 block period with a 25G PCS transmission period (in units of 2-8 ns). The code should be adjusted for the appropriate data rate as necessary.