Register Spaces - 1.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2021-02-05
Version
1.3 English

All the control and status registers are memory mapped. After power-up or reset, you can reconfigure the core parameters from their defaults at any time. Access type details are given in Table-4. Table-5 has the register map details

Table 1. Register access type definitions
Acess Type Description

RO

Read Only

Readable register; write has no effect

RW

Read-Write

Readable and writable register

RW1T

Read Write ‘1’ to trigger

Write ‘1’ to trigger. Write ‘0’ is ignored. Read returns ‘0’.

RW1C

Read, write ‘1’s to Clear

Writing a ‘1’ clears the corresponding bit position in the register to ‘0’; Writing a ‘0’ leaves the corresponding bit unchanged.

For example, it can be used to acknowledge interrupt status.

WO

Write Only

Writable register, the value is not readable (returns ‘0’)

Table 2. Register Map
Offset Register Name Access Description
0x0000 TOD_CONFIG RW

Main Configuration

[0] – Enable System Timer

A ‘0’ to this bitfield disables the system timer IP.

[1] – Enable External ToD Bus

Write ‘1’ to enable the ToD Bus signals. The Overwrite Mode field further defines how signaling is used.

This is present only when the core is generated with External ToD Bus I/F support

[3:2] – Overwrite Mode:

• 0x0 - System Timer counter is not overwritten at 1-PPS event from External ToD Bus.

• 0x1 - System Timer counter is overwritten with the External ToD Bus seconds input at 1-PPS event from External ToD Bus.

• 0x2 - System Timer counter is overwritten with value stored in the SW TOD_SW_SEC_0/1 register at 1-PPS event from the External ToD Bus.

• 0x3 - Reserved.

The above Modes are only present when the core is generated with Ext ToD Bus interfacce support

[4 to 19] – Enable Port TX and RX Timers

• [4] = Enable Port-0 TX and RX

• [5] = Enable Port-1 TX and RX

…….

• [16] = Enable Port-15 TX and RX

The upper limit for port number depends on the number of ports enabled at the time of generating core.

[31:20] - Reserved

0x0004 TOD_SNAPSHOT RW1T

[0] – Snapshot all timers

Writing 1’b1 snapshots all Counters (System, External ToD Bus, and all enabled ports)

[31:1] = Reserved

0x0008 TOD_INTR_ENABLE RW

Interrupt enable register

[0] = 1-PPS interrupt

[31:1] = Reserved

0x000C TOD_INTR_STATUS RW1C

Interrupt clear register

[0] = 1-PPS interrupt

[31:1] = Reserved

0x0010 TOD_SW_SEC_0 RW [31:0] = Overwrite Master Timer’s Second field bits [31:0]
0x0014 TOD_SW_SEC_1 RW

[15:0] = Overwrite Master Timer’s Second field bits [47:32]

[31:16] = Reserved

0x0018 TOD_SW_NS RW

[29:0] = Overwrite Master Timer’s Second field bits

[31:30] = Reserved

0x001C TOD_SW_LOAD RW1T

[0] - Write ‘1’ Initiates a load of the System Timer’s ToD values from the TOD_SW_SEC_0/1, TOD_SW_NS, and TOD_SW_CTIME_0/1 registers.

[1] - Write ‘1’ initiates a load of the System Timer’s ToD Offset value from the TOD_SEC_SYS_OFFSET_0/1, and TOD_NS_SYS_OFFSET_0 registers.

Note: Offset is added by logic prior to System Timer’s output to the Port Timers. As such, Offset is not reflected by System Timer ToD read backs.

[31:0] - Reserved

0x0020 TOD_SW_CTIME_0 RW [31:0] = Overwrite Master Timer’s CF field bits [31:0]
0x0024 TOD_SW_CTIME_1 RW

[30:0] = Overwrite Master Timer’s Second field bits [63:32]

[31] = Reserved

0x0028 TOD_SEC_SYS_OFFSET_0 RW

{TOD_SEC_SYS_OFFSET_1[15:0], TOD_SEC_SYS_OFFSET_0[31:0]} - Represents System timer 48b seconds field signed offset value.

TOD_NS_SYS_OFFSET_0[29:0] - Represents System timer 30b nano second field signed offset value.

Signed bit interpreted as follows for TOD_SEC_SYS_OFFSET:

If [47] = 1’b1 then subtract from system timer

If [47] = 1’b0 then add to system timer

Need to apply trigger bit [1] at register 0x001C

0x002C TOD_SEC_SYS_OFFSET_1 RW
0x0030 TOD_NS_SYS_OFFSET_0 RW
0x0100 TOD_SYS_SEC_0 RO Snapshot of System Timer’s Second Field [31:0]
0x0104 TOD_SYS_SEC_1 RO

[15:0] = Snapshot of System Timer’s Second Field [47:32]

[31:16] = Reserved

0x0108 TOD_SYS_NS RO

[29:0] = Snapshot of System Timer’s Nano-second Field [29:0]

[31:30] = Reserved

0x010C TOD_SYS_OFFSET RW

[31:0] - Signed offset to be applied to seconds value loaded from the External ToD bus, and to be added to 0 nanoseconds field when a 1PPS event occurs on the External ToD bus.

The signed value is expressed in 2-16 ns.

This is present only when the core is generated with Ext ToD Bus support

0x0110 TOD_SYS_CTIME_0 RO Snapshot of System Timer’s CF Field [31:0]
0x0114 TOD_SYS_CTIME_1 RO

[30:0] = Snapshot of System Timer’s CF Field [63:32]

[31] = Reserved

0x0120 TODBUS_SEC_0 RO Current value of the Ext ToD Bus’s Second Field [31:0]
0x0124 TODBUS_SEC_1 RO

[15:0] = Current value of the Ext ToD Bus’s Second Field [47:32]

[31:16] = Reserved

0x012C

TODBUS_SYS_DIFF

RO [31:0] - Once a second comparison of External ToD bus captured value and System Timer’s internal ToD value in signed unit of 2-16 ns
Port registers: These are preset only in the Timer Syncer mode or in Syncer mode
Port 0 Registers: 0x0200 to 0x023F
0x0200 TX0_CTIME_0 RW Snapshot of Port0 TX Timer’s CF Field [31:0]
0x0204 TX0_CTIME_1 RW

[30:0] = Snapshot of Port0 TX Timer’s CF Field [63:32]

[31] = Reserved

0x0208 TX0_PERIOD_0 RW

Port0 TX clock period expressed in 2-48 ns

For example, 3.2 ns is represented as

TX0_PERIOD_0 = 0x3333_3333

TX0_PERIOD_1 = 0x0003_3333

TX0_PERIOD_1[31:24] reserved

0x020C TX0_PERIOD_1 RW
0x0210 TX0_SYS_OFFSET

RW

[31:0]- Signed offset applied to Port0 TX Timer’s o/p expressed in 2-16 ns.
0x0214 TX0_NS_SNAP RO

[29:0] = Snapshot of Port0 TX Timer’s Nano-second Field [29:0]

[31:30] = Reserved

0x0218 TX0_SEC_0_SNAP RO [31:0]- Snapshot of Port0 TX Timer’s Second Field [31:0]
0x021C TX0_SEC_1_SNAP RO

[15:0] = Snapshot of Port0 TX Timer’s Second Field [47:32]

[31:16] = Reserved

0x0220 RX0_CTIME_0 RW Snapshot of Port0 RX Timer’s CF Field [31:0]
0x0224 RX0_CTIME_1 RW

[30:0] = Snapshot of Port0 RX Timer’s CF Field [63:32]

[31] = Reserved

0x0228 RX0_PERIOD_0 RW

Port0 RX clock period expressed in 2-48 ns

For example, 3.2 ns is represented as

RX0_PERIOD_0 = 0x3333_3333

RX0_PERIOD_1 = 0x0003_3333

RX0_PERIOD_1[31:24] reserved

0x022C RX0_PERIOD_1 RW
0x0230 RX0_SYS_OFFSET RW Signed offset applied to Port0 RX Timer’s o/p expressed in 2-16 ns.
0x0234 RX0_NS_SNAP RO

[29:0] = Snapshot of Port0 RX Timer’s Nano-second Field [29:0]

[31:30] = Reserved

0x0238 RX0_SEC_0_SNAP RO Snapshot of Port0 RX Timer’s Second Field [31:0]
0x023C RX0_SEC_1_SNAP RO

[15:0] = Snapshot of Port0 RX Timer’s Second Field [47:32]

[31:16] = Reserved

Port 1 Registers: 0x0240 to 0x027F
Port 2 Registers: 0x0280 to 0x02BF
Port 3 Registers: 0x02C0 to 0x02FF
Port 4 Registers: 0x0300 to 0x033F
Port 5 Registers: 0x0340 to 0x027F
Port 6 Registers: 0x0380 to 0x03BF
Port 7 Registers: 0x03C0 to 0x03FF
Port 8 Registers: 0x0400 to 0x043F
Port 9 Registers: 0x0440 to 0x047F
Port 10 Registers: 0x0480 to 0x04BF
Port 11 Registers: 0x04C0 to 0x04FF
Port 12 Registers: 0x0500 to 0x053F
Port 13 Registers: 0x0540 to 0x057F
Port 14 Registers: 0x0580 to 0x05BF
Port 15 Registers: 0x05C0 to 0x05FF