Reset pins and RESET_REG bits other than
rx_serdes_reset are for debugging purpose only. It should not be asserted
by the user logic.
|MRMAC Reset Pin||Associated RESET_REG Bits (Per Port)||Description|
|Per-port TX and RX core reset.
Asserting the reset resets the entire RX or TX datapath for that port including:
|rx_serdes_reset[3:0]||rx_serdes_reset[N:0]||Per-port RX SerDes (GT) interface reset.
The RX SerDes can be reset through the register interface on a per-port basis. However, different ports have different allowable configurations and hence there are different reset fields depending on the port. Consequently, each port's RESET_REG has an N-bit rx_serdes_reset field, where N represents the number of PHY lanes present for a Port's configuration.
For example, Port 0 can support operation up to and including 100G (requiring four SerDes) and so the reset field is four bits wide. However, if the port were to be configured as 50G, only rx_serdes_reset[1:0] would be in use.
Meanwhile, Port 1 only supports lower speed operation and so it is directly tied to a SerDes instance. Therefore, there is only one active reset bit (rx_serdes_reset).
|tx_serdes_reset[3:0]||tx_serdes_reset||Per-port TX SerDes (GT) interface reset.
A single reset port resets each of the TX GT interface logic. For example, tx_serdes_reset resets all of the GT interface logic for Port 0, regardless of configuration.
|apb3_preset||Resets the AXI4-Lite port logic, status, and statistics registers.|
The following ports are used for Versal GT reset control.
s_axi_aclk is also used as a free running clock for reset
|I||Reset input to Reset IP. It resets PLL and data-path.|
|I||TX PMA Reset done from GT|
|I||RX PMA Reset done from GT|
|I||TX Master Reset done from GT|
|mst_rx_resetdone_in[3:0]||I||RX Master Reset done from GT|
|gtpowergood_in||I||Power Good from GT|
|txuserrdy_out[3:0]||O||TX User Ready to GT|
|O||RX User Ready to GT|
|O||TX Master Reset to GT|
|O||RX Master Reset to GT|
The clock and reset connection between MRMAC and GT is shown in the following figure.