- Once the bitstream (.pdi) and the application file (.elf) are ready, power
ON the Versal board.
Ensure that all power UART and loopback cable connections are properly connected. Refer to the VCK190 Evaluation Board User Guide (UG1366) and VMK180 Evaluation Board User Guide (UG1411) for additional information.
- Before dumping the MRMAC image, configure the device with the required
reference frequency, as shown in the following figure. Clock programming files
can be obtained through the Versal
- Launch the Vivado hardware manager.
Select the Versal device and program the
- Launch the Vivado Lab Edition, and click Open Hardware Manager.
- Select .
- Right click vjtag40_1, and select Program Device as shown in the following figure.
- Browse to the path where the bitstream (.pdi) is located, and then select Program.
- Open the xsdb console in C:\Xilinx\Vivado_Lab\2020.1\bin. Follow the procedure as shown
in the following snapshot and observe the results in Tera
Note: Set the .elf file path before downloading .elf.
See the results in Tera Term.