DPU Naming - 1.3 English

Vitis AI User Guide (UG1414)
Document ID
UG1414
Release Date
2021-02-03
Version
1.3 English

Vitis AI 1.2 and later releases use a new DPU naming scheme to differentiate various DPUs designed for different purposes. The old DPUv1/v2/v3 naming is deprecated.

The new DPU naming convention is shown in the following figure:

Figure 1. DPU Naming Convention

DPU Naming Example

To understand the mapping between the old DPU naming scheme and the current naming scheme, see the following table:

Table 1. DPU Naming Examples
Example DPU Application Hardware Platform Quantization Method Quantization Bitwidth Design Target Major Minor Patch DPU Name
DPUv1 DPU C AD X 8 G 3 0 0 DPUCADX8G-3.0.0
DPUv2 DPU C ZD X 8 G 1 4 1 DPUCZDX8G-1.4.1
DPUv3e DPU C AH X 8 H 1 0 0 DPUCAHX8H-1.0.0
DPUv3me DPU C AH X 8 L 1 0 0 DPUCAHX8L-1.0.0
DPUv3int8 DPU C AD F 8 H 1 0 0 DPUCADF8H-1.0.0
XRNN DPU R AH R 16 L 1 0 0 DPURAHR16L-1.0.0
  1. For Application: C-CNN, R-RNN
  2. For Hardware Platform: AD-Alveo DDR; AH-Alveo HBM; VD-Versal DDR with AI Engine and PL; ZD-Zynq DDR
  3. For Quantization method: X-Decent; F- Float threshold; I-Integer threshold; R-RNN
  4. For Quantization bandwidth: 4-4 bit; 8-8 bit; 16-16 bit; M- Mixed precision
  5. For Design target: G-General purpose; H-High throughput; L-Low latency; C-Cost optimized