The Vitis™ AI compiler (VAI_C) is the unified interface to a compiler family targeting the optimization of neural-network computations to a family of DPUs. Each compiler maps a network model to a highly optimized DPU instruction sequence.
The simplified description of VAI_C framework is shown in the following figure. After parsing the topology of optimized and quantized input model, VAI_C constructs an internal computation graph as intermediate representation (IR). Therefore, a corresponding control flow and a data flow representation. It then performs multiple optimizations, for example, computation nodes fusion such as when batch norm is fused into a presiding convolution, efficient instruction scheduling by exploit inherent parallelism, or exploiting data reuse.
The Vitis AI Compiler generates the compiled model based on the DPU microarchitecture. There are a number of different DPUs supported in Vitis AI for different platforms and applications. It is important to understand the relations between available compilers and associate DPUs. See DPU Naming for the DPU naming scheme.
To better understand how to map the compilers with DPUs, please refer to the following table.
| DPU Name | Compiler | Hardware platform |
|---|---|---|
| DPUCZDX8G | XCompiler | Zynq UltraScale+ MPSoC, Zynq-7000 devices |
| DPUCAHX8H | U50, U280 | |
| DPUCAHX8L | U50, U280 | |
| DPUCADF8H | U200, U250 | |
| DPUCVDX8G | VCK190, Versal AI Core Series | |
| DPUCVDX8H | VCK5000 | |
| DPUCADX8G | xfDNN Compiler | U200, U250 |
XCompiler stands for XIR based Compiler. It can support DPUCZDX8G, DPUCAHX8H, DPUCAHX8L, DPUCVDX8G and DPUCVDX8H. xfDNN Compiler is the compiler from the legacy ML Suite which supports DPUCADX8G only. This has been retained in the Vitis AI 1.3 release for backward compatibility and will be deprecated in the Vitis AI 1.4 release.