Vitis™ AI VAI_C is the unified interface to a compiler family targeting for the optimization of neural-network computations to a family of DPUs. Each compiler maps a network model into a highly optimized DPU instruction sequence.
The simplified description of VAI_C framework is shown in the following figure. After parsing the topology of optimized and quantized input model, VAI_C constructs an internal computation graph as intermediate representation (IR). Therefore, a corresponding control flow and a data flow representation. It then performs multiple optimizations, for example, computation nodes fusion such as when batch norm is fused into a presiding convolution, efficient instruction scheduling by exploit inherent parallelism, or exploiting data reuse.