The DPUCZDX8G IP has been optimized for Xilinx MPSoC devices. This IP can be integrated as a block in the programmable logic (PL) of the selected Zynq-7000 SoC and Zynq UltraScale+ MPSoCs with direct connections to the processing system (PS). The configurable version DPU IP is released together with Vitis AI. DPU is user-configurable and exposes several parameters which can be specified to optimize PL resources or customize enabled features. If you want to perform a DPU IP integration to create the customized AI projects or products, see the https://github.com/Xilinx/Vitis-AI/tree/master/DPU-TRD.
Figure 1.
DPUCZDX8G Architecture
