The Vitis™ AI compiler (VAI_C) is the unified interface to a compiler family targeting the optimization of neural-network computations to a family of DPUs. Each compiler maps a network model to a highly optimized DPU instruction sequence.
The simplified description of VAI_C framework is shown in the following figure. After parsing the topology of optimized and quantized input model, VAI_C constructs an internal computation graph as intermediate representation (IR). Therefore, a corresponding control flow and a data flow representation. It then performs multiple optimizations, for example, computation nodes fusion such as when batch norm is fused into a presiding convolution, efficient instruction scheduling by exploit inherent parallelism, or exploiting data reuse.
The Vitis AI Compiler generates the compiled model based on the DPU microarchitecture. Vitis AI supports several DPUs for different platforms and applications.
|DPU Name||Hardware platform|
|DPUCZDX8G||Zynq® UltraScale+™ MPSoC|
|DPUCAHX8H||Alveo™ U50, U280 Data Center accelerator cards|
|DPUCAHX8L||Alveo U50, U280 Data Center accelerator cards|
|DPUCADF8H||Alveo U200, U250 Data Center accelerator cards|
|DPUCVDX8G||Versal® ACAP VCK190 evaluation board, Versal AI Core Series|
|DPUCVDX8H||Versal ACAP VCK5000 evaluation kit|