The AXI4-Lite interface has its own
clock and reset. The AXI4-Lite clock (
s_axi_aclk) is independent of the remainder of the MRMAC clocks and can be any frequency to a maximum of
Asserting the AXI4-Lite
s_axi_areset pin results in:
- A reset of the AXI4-Lite port and MRMAC APB3 control logic, stopping any in-flight writes/reads.
- A reset of the current accumulated statistics and status registers for all slices. If only the AXI4-Lite port reset is asserted, then the internal statistics and status engines immediately begins monitoring the MRMAC operation and restarts the accumulations of the statistics counters.
- A reset of all ports in User Scratch registers: USER_REG_0-3 to
- A reset of all ports in Reset registers: RESET_REG_0-3 to
An AXI4-Lite reset does not reset the internal configuration registers.
In addition to the
statistics and status registers require a port's core clock (
tx_core_clk[N]) be active
and stable to operate. Unless the entire MRMAC
is held in reset, all AXI4-Lite write/read transaction
completes without asserting an
s_axi_pslverr. If the
s_axi_pslv_err is asserted, an event such as an unstable
AXI4-Lite or core clock during a transaction has
occurred, and the MRMAC must be reset.
If the AXI4-Lite port attempts a read
or write access to the memory space of a disabled port (for example, ports with their clock
tied to 0/1 or which are held in reset) or to a non-existent register address, the
transaction completes and one of the debug signals
stat_rsvd_out[179:178] toggle for one
s_axi_aclk cycle. In such cases, the value on the AXI4-Lite port’s output is invalid.