Typical Flex I/F TX and RX transactions can be seen in the following diagrams.
In this example, data transfer into the Flex I/F port is active on Client 0. The user logic
drives data (
tx_flex_data2) into the
interface while asserting
Note the relationship between the per-port
tx_flex_stall_<N> signal and
The stall signal is output to backpressure the transfers into the Flex I/F. The interface
requires that you suspend transfers (
tx_flex_enain == 0) exactly
three cycles after the
tx_flex_stall_<N> is asserted to
tx_flex_alignmarker<N>to indicate that the data includes an AM. This prevents the scrambler from scrambling the alignment markers.
rx_flex_ena_<N>is deasserted, the data is invalid. Note that there is no backpressure from the user logic back to the Flex I/F port. The user logic should be able to keep up with the selected data rate.