This product guide describes the function and operation of the Xilinx® Versal® devices integrated 100G Multirate Ethernet MAC subsystem, including how to design, customize, and implement the MRMAC.
The MRMAC subsystem handles all protocol related functions of an Ethernet MAC, PCS, and FEC, including handshaking, synchronizing, and error checking. An AXI4-Stream interface is provided for packet data, and an AXI4-Lite interface is provided for statistics and management.
The subsystem can provide up to four independent Ethernet ports and is designed to be flexible for use in many different applications. To reduce latency, the datapath does not perform any buffering other than the pipelining required to perform the required operations. Received data is passed directly to the user interface in a cut-through manner, and allowing the flexibility to implement any required buffering scheme. Similarly, the transmit path consists of minimal pipeline and buffering to provide reliable cut-through operation.
The MRMAC subsystem can be configured to include forward error correction (FEC).
The following lists the supported rates, FEC types, and configurations:
|Data Rates||Data Path Functions||Integrated PCS Options|
|1 × 100GE 1||MAC+PCS, PCS Only||No FEC, IEEE 802.3 CL91 RS(528,514) “KR4” FEC and CL91 RS(544,514) “KP4” FEC|
|2 × 50GE 1||No FEC, IEEE 802.3 CL134 RS(544,514) “KP4” FEC, 25/50GE Consortium RSFEC/CL74 FEC|
|1 × 40GE 1||No FEC, IEEE 802.3 CL74 FEC|
|4 × 25GE 1||No FEC, IEEE 802.3 CL108 and 25/50GE Consortium RS(528,514) FEC, CL74 FEC|
|4 × 10GE 1||No FEC, IEEE 802.3 CL74 FEC|
|4 × FC32 1||FEC Only||N/A|
|1 x 106.2GE (Overclocked 100GE) 1||Same as 100GE||Same as 100GE|
|1 x 112.84G FEC Only||FEC Only||IEEE 802.3 CL91 RS(528,514)
"KR4" FEC and CL91 RS(544,514) "KP4" FEC
|2 x 56.42G FEC Only 1||FEC Only||IEEE 802.3 CL134 RS(544,514)
“KP4” FEC, 50GE Consortium "KR4" RSFEC
|1 x 64GFC||FEC Only (requires additional programmable logic)||CL91 RS(544,514) "KP4" FEC|
|2 x 64GFC2||FEC Only (requires additional programmable logic)||CL91 RS(544,514) "KP4" FEC|
- Port 0 : 100 GbE with/without FEC
- Port 0 : 50 GbE with/without FEC
- Port 0 and Port 2 : 25 GbE with/without FEC
- Port 1 and Port 3 : 25 GbE without FEC
- Other port settings for FEC are not valid.
- These restrictions do not apply to Production Silicon.