The following describes the transmit clocks in the MRMAC.
- This internal high-speed clock drives the bulk of the MRMAC transmit datapath. This per-port clock must be generated by the GT transceiver.
- This is an internally-used clock derived from the primary SerDes
clocks. These clocks run at exactly half the
tx_core_clk[3:0]frequencies. This clock is typically generated by the IP Wizard.
- This is used by the flex interface. When the Flex I/F is active,
tx_flexif_clk[N]must operate at a frequency ≥ 1/2 of the corresponding
AXI4-Stream interface clocks. In
addition to clocking the AXI4-Stream interface in
independent clocking mode, the
tx_axi_clkclocks are also used only to clock certain statistics and flow control signals. The
tx_axi_clkclocks must operate at a frequency high enough to maintain the desired data rate across the AXI4-Stream bus, which is
tx_axi_clk[N]must be greater than or equal to 1/2 of the corresponding
- This clock drives the 1588 timestamping signaling. The MRMAC timestamp timers attempt to synchronize with the external time-of-day source which is running on this clock.
|Selected Data Rate||AXI Clock Minimum Frequency (MHz)||AXI4-Stream Segment Mode||Port AXI4-Stream MODE_REG Field ctl_axis_cfg_<N>|