Introduction - 1.2 English

HDMI 2.1 Receiver Subsystem v1.2 Product Guide (PG351)
Document ID
PG351
Release Date
2023-10-31
Version
1.2 English

The HDMI 2.1 Receiver Subsystem takes in HDMI™ 2.1 protocol video and works with the HDMI PHY Controller/HDMI GT Subsystem. For more information, see the HDMI PHY Controller LogiCORE IP Product Guide (PG333) / HDMI GT Controller LogiCORE IP Product Guide (PG334) .

Note: The HDMI GT Subsystem is comprised of the HDMI GT Controller IP and the Versal adaptive SoC Transceivers Wizard IP. For more information, see HDMI GT Controller LogiCORE IP Product Guide (PG334).

The HDMI 2.1 RX Subsystem is hierarchically packaged with the following subcores to support AXI4-Stream based video and works seamlessly with other AMD video processing IP cores.

  • HDMI 2.1 Receiver core
  • Video In to AXI4-Stream Bridge
  • AXI Remapper RX

The subsystem also includes an optional HDCP 2.3 controller and HDCP 1.4 controller (together with an AXI Timer core as a helper core) for HDCP 2.3 or HDCP 1.4 decryption functionality.

You can configure it by setting the parameters in the AMD Vivado™ Integrated Design Environment (IDE) interface and the subsystem creates the required hardware accordingly. The following figures show the architecture of the subsystem. The HDMI 2.1 RX subsystem supports the following types of video interface:

  • AXI4-Stream Video interface
  • Native Video interface
  • Native Video (Vectored Data Enable (DE)) interface

The following table summarizes the supported video timing for each interface, depending on the PPC settings.

Table 1. Supported Video Timing
Video Interface Color Space Pixels Per Clock (PPC)
4 8
AXI4-Stream RGB,YCbCr 444, YCbCr 422 HACTIVE should be divisible by 4. HACTIVE should be divisible by 8.
YCbCr 420 HACTIVE should be divisible by 8.
Native Video RGB,YCbCr 444, YCbCr 422 HACTIVE, HSYNC, HTOTAL should be divisible by 4. Not applicable (Always 4 PPC).
YCbCr 420
Native Video (Vectored DE) RGB,YCbCr 444, YCbCr 422 No restrictions. All combinations are supported.
YCbCr 420
  1. AXI4-Stream and Native Video (Vectored DE) I/F supports all CTA resolutions.
  2. In Native Video I/F, due to the divisible by PPC restriction, all CTA resolutions are not supported.
Important: The IP supports 8kp48, 8kp50, and 8kp60/10kp60 YUV420 in both Native Video, Native Video (Vectored DE), and AXI4-Stream interfaces. To enable 8kp48, 8kp50, and 8kp60/10kp60 YUV420 support in AXI4-Stream Mode, select Number of pixels per clock as 8. In Native Video or Native Video (Vectored DE) Interface, 4 PPC supports 8kp48, 8kp50, and 8kp60/10kp60 YUV420.
Important: In Native Video or Native Video (Vectored DE) Interface, the IP supports YCbCr 4:2:0. However, you must process YCbCr 4:2:0 Pixel Encoding. See Section 7 in the HDMI 2.0b Specification (https://www.hdmi.org/spec/index) or AXI4-Stream Video Output Stream Interface.
Important: The HDMI 2.1 Receiver Subsystem IP supports pixel repetition of 2, when the AXI4-Stream Video interface is selected. However, it has the limitation of supporting only RGB and YUV444 color space, but not YUV422. Therefore, when AXI4-Stream is used, pixel repetition of 2 is supported. The repeated pixel is dropped by the HDMI 2.1 Receiver Subsystem. When the Native/Native DE interface is used, none of the pixels are dropped. All pixels are sent through native video output interface, which you can use to create customized pixel replication logic to support all color spaces including 12-bit YUV422.
Figure 1. HDMI 2.1 RX Subsystem AXI4-Stream Video Interface Block Diagram
Figure 2. HDMI 2.1 RX Subsystem Native Video or Native Video DE Interface Block Diagram