Reference Clock

Versal ACAP GTM Transceivers Architecture Manual (AM017)
Document ID
AM017
Release Date
2022-04-27
Revision
1.0 English

This section focuses on the selection of the reference clock source or oscillator. An oscillator is characterized by:

  • Frequency range
  • Output voltage swing
  • Jitter (deterministic, random, peak-to-peak)
  • Rise and fall times
  • Supply voltage and current
  • Noise specification
  • Duty cycle and duty-cycle tolerance
  • Frequency stability

These characteristics are selection criteria when choosing an oscillator for a GTM transceiver design. Figure 1 illustrates the convention for the single-ended clock input voltage swing, peak-to-peak. This figure is provided to show the contrast to the differential clock input voltage swing calculation shown in Figure 2, as used in the GTM transceiver portion of the Versal ACAP data sheets.

Figure 1. Single-Ended Clock Input Voltage Swing, Peak-to-Peak

The following figure illustrates the differential clock input voltage swing, which is defined as GTM_REFCLKP/GTM_GTREFCLKN.

Figure 2. Differential Clock Input Voltage Swing, Peak-to-Peak

The following figure shows the rise and fall time convention of the reference clock.

Figure 3. Rise and Fall Times

The following figure illustrates the internal details of the IBUFDS. The dedicated differential reference clock input pair GTM_REFCLKP/GTM_REFCLKN is internally terminated with 100Ω differential impedance. The common mode voltage of this differential reference clock input pair is GTM_AVCC, 0.8V. See the Versal ACAP data sheets for exact specifications.

Figure 4. MGTREFCLK Input Buffer Details

Notes:

  1. The resistor values are nominal. See the Versal ACAP data sheets for exact specifications.
  2. AC mode is shown. In DC mode, the internal terminating resistors are not connected. For DC mode, external terminating resistors are required.