The RX clock divider control block has two main components: serial clock divider control and parallel clock divider and selector control. The clock divider and selector details are illustrated in the figure below.
Figure 1. RX Serial and Parallel Clock Divider
Notes related to the figure:
- CH*_RXOUTCLK is used as the source of the interconnect logic clock via BUFG_GT.
- For details about placement constraints and restrictions on clocking resources (such as BUFG_GT and BUFG_GT_SYNC), refer to the Versal ACAP Clocking Resources Architecture Manual (AM003).
- The clock output from IBUFDS_GTE5 should only be used after GTPOWERGOOD asserts High.