Port Names - 1.0 English

I2S Transmitter and I2S Receiver LogiCORE IP Product Guide (PG308)

Document ID
PG308
Release Date
2021-11-10
Version
1.0 English
Table 1. Port Names
Port Name I/O Clock Description
Transmitter Ports
s_axi_ctrl_aclk I Clock Input clock for AXI4-Lite Interface
s_axi_ctrl_aresetn I Reset Active-Low reset for AXI4-Lite Interface
s_axi_ctrl_*   s_axi_ctrl AXI4-Lite Interface
aud_mclk I Clock Input audio clock. Typically a multiple of Fs.
aud_mrst I Reset Active-High reset for audio interface
s_axis_aud_aclk I Clock AXIS Audio streaming clock
s_axis_aud_resetn I Reset Active-Low AXIS audio reset
s_axis_aud_*   Audio AXIS Interface AXIS audio interface 1
Irq O Interrupt Active-High interrupt
lrclk_out O LRClk Output LR Clock. Available when core is configured as Master.
sclk_out O SCLK Output SCK Clock. Available when core is configured as Master.
lrclk_in I LRClk Input LR Clock. Available when core is configured as Slave.
Sclk_in I SCLK Input SCK Clock. Available when core is configured as Slave.
sdata_0_out O SDATA0 I2S Serial Data out
sdata_1_out O SDATA1 I2S Serial Data out. Available when number of audio channels is > 2.
sdata_2_out O SDATA2 I2S Serial Data out. Available when number of audio channels is > 4.
sdata_3_out O SDATA3 I2S Serial Data out. Available when number of audio channels is > 6.
Receiver Ports
s_axi_ctrl_aclk I Clock Input clock for AXI4-Lite Interface
s_axi_ctrl_aresetn I Reset Active-Low reset for AXI4-Lite Interface
s_axi_ctrl_*   s_axi_ctrl AXI4-Lite Interface
aud_mclk I Clock Input audio clock. Typically a multiple of Fs.
aud_mrst I Reset Active-High reset for audio interface
m_axis_aud_aclk I Clock AXIS Audio streaming clock
m_axis_aud_resetn I Reset Active-Low AXIS audio reset
m_axis_aud_*   Audio AXIS Interface AXIS Audio Interface 1
Irq O Interrupt Active-High interrupt
lrclk_out O LRClk Output LR Clock. Available when core is configured as master.
sclk_out O SCLK Output SCK Clock. Available when core is configured as master.
lrclk_in I LRClk Input LR Clock. Available when core is configured as slave.
Sclk_in I SCLK Input SCK Clock. Available when core is configured as slave.
sdata_0_in I SDATA0 I2S Serial Data In
sdata_1_in I SDATA1 I2S Serial Data In. Available when number of audio channels is > 2.
sdata_2_in I SDATA2 I2S Serial Data In. Available when number of audio channels is > 4.
sdata_3_in I SDATA3 I2S Serial Data In. Available when number of audio channels is > 6.
  1. For more details on Audio AXIS interface, see Audio AXIS Interface.