| s_axis_h2c_tdata[C_M_AXI_DATA_WIDTH-1:0] |
I |
Data input for H2C AXI4-Stream
|
| s_axis_h2c_qid[10:0] |
I |
Queue ID |
| s_axis_h2c_port_id[2:0] |
I |
Port ID |
| s_axis_h2c_err |
I |
If set, indicates the packet has an error. This
error could be from PCIe, or the
QDMA might have encountered a double bit error. |
| s_axis_h2c_mdata[31:0] |
I |
Metadata |
| s_axis_h2c_mty[5:0] |
I |
The number of bytes that are invalid on the last
beat of the transaction. |
| s_axis_h2c_zero_byte |
I |
When set, it indicates that the current beat is
empty beat (zero bytes are being transferred) |
| s_axis_h2c_tvalid |
I |
Valid |
| s_axis_h2c_tlast |
I |
Indicates last cycle of the packet
transfer |
| s_axis_h2c_tready |
O |
Ready |
| s_axis_h2c_tcrc[31:0] |
I |
32-bit CRC value of that beat, IEEE 802.3 CRC-32
Polynomial |