Constraining the Core - 2.0 English

Required Constraints

This section is not applicable for this IP core.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

Clock Frequencies

This IP needs two clocks:

• A software clock sw_s_axi_lite_aclk with a frequency of 100 MHz.
• A host interface clock core_clk which is the output of the QDMA.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.