This module implements the controller registers described in NVM Express 1.3 specification for each VF/PF function. Please refer to section 3.1 of the NVMe 1.3 specification for details on the controller registers.
The QDMA IP allows for one or more PCIe BAR
of any function to be mapped to the AXI4-Lite
interface of the IP. This interface is mapped to the
host_s_axi_lite (slave) interface of the NVMe TC IP. The QDMA
configuration is done at the time of IP generation. In order for a seamless integration
between QDMA and NVMe TC, all VF and PF BAR0 and BAR1 need to be mapped to the AXI4-Lite bridge interface of the QDMA. Function ID, bar id
(bar hit), VF group, and VF group offset is available from the QDMA as a part of ARUSER
and AWUSER of the AXI4-Lite interface and is used by
the NVMe TC to identify the source of the memory access.
The Control and Status Register (CSR) modules also implements the NVMe TC specific configuration registers.