Global Ports - 2.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)

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2.0 English
Table 1. NVMe Global Port Descriptions
Port Name I/O Description
core_clk I Core clock
core_rstn I Active-Low reset for core_clk
nvme_tc_intr O Interrupt
sw_s_axi_lite_aclk I AXI4-Lite clock
sw_s_axi_lite_aresetn I Active-Low reset for sw_s_axi_lite_aclk
pcie_link_up I Active-High identifies that the PCI Express core is linked up with a host device
pcie_phy_ready I Phy ready out status
soft_reset_n O Soft reset (active-Low). Use this port to assert reset and reset the DMA logic in QDMA. This only resets the DMA logic.