Introduction - 2.0 English

The Xilinx® NVMe™ Target Controller IP allows for the implementation of a Non-Volatile Memory Express (NVMe) device inside an FPGA. The IP works in tandem with the Xilinx QDMA Subsystem for PCI™ Express and exposes an NVMe 1.3 spec compliant device view to the host. The IP manages the following functions:

1. Exposes and emulates the NVMe controller registers as defined in the NVMe 1.3 specification.
2. Manages the Submission Queue (SQ)/Completion Queue (CQ) doorbells from the host.
3. Arbitrates across available SQs and programs the Queue Direct Memory Access (QDMA) to fetch the required submission queue entries (SQEs).
4. Parses the SQEs and programs the QDMA to fetch the physical region page (PRP) list if applicable.
5. Programs the QDMA for data transfer between host and FPGA (for reads or writes) based on instruction from the application/user logic.
6. Programs the QDMA for completion queue entry (CQE) transfer to the host based on instruction from the application/user logic.

The following sections provide a top-level description of the IP along with its interfaces and programing information. The terms “flash drives”, “NVMe drives” and “SSDs” are used interchangeably in the document and signify an NVMe based flash device used for storage.