The NVMe™ Target Controller core interfaces with QDMA on the host facing side and with the hardware application, processor, and DDR (or any memory region) on the FPGA facing side. The NVMe TC IP maps the admin queues of all PCIe® functions to the software interface and I/O queues of all functions to the hardware interface. The IP manages all control paths and programs the QDMA for SQE fetches (and PRP fetches, if required), CQE writes, and all data transfers. The figure below shows the top-level diagram of the NVMe TC IP and the various interfaces it exposes.
Figure 1. NVMe Target Controller Block Diagram
