All NVMe TC IP registers are accessible via AXI4-Lite interface.
Any bits not specified in the following register tables are considered reserved and return 0 upon being read. The power on reset values of control registers are 0, unless it is specified in the definition.
Only address offsets are listed in the following table; the base address is configured by the AXI interconnect at system level.
Depending on the number of functions supported (as defined by the parameter C_MAX_FUNC), the register space of the NVMe TC IP would vary. However, the NVMe TC IP control and status registers are common across the functions and do not change based on parameter.