Scaling Down the Frequency of the DPU - 2.0 English

Due to the power limitation of the card, sometimes frequency scaling-down operation is necessary.

The DPU core clock is generated from an internal DCM module driven by the platform Clock_1 with the default value of 100 MHz, and the core clock is always linearly proportional to Clock_1. For example, in the U50LV-10E275M overlay, the 275 MHz core clock is driven by the 100 MHz clock source. To set the core clock of this overlay to 192.5 MHz, set the frequency of Clock_1 to (192.5/275)*100 = 70 MHz.

You can use the XRT xbutil tools to scale down the running frequency of the DPU overlay before you run the VART/Library examples. Before the frequency scaling-down operation, the overlays should be programmed into the FPGA first. Refer to the following example commands to program the FPGA and scale down the frequency. These commands will set the Clock_1 to 80 MHz and can be run at host or in the Docker.

/opt/xilinx/xrt/bin/xbutil reset -d <user bdf>
/opt/xilinx/xrt/bin/xbutil program -d <user bdf> -u <xclbin path>
/opt/xilinx/xrt/bin/xbutil --legacy clock -d <user bdf> -g 70

For more information on the xbutil tool, see the XRT documents. <xclbin path> is the full path of the corresponding xclbin file, usually from /opt/xilinx/overlaybins.