Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
- Machine Learning and Data Science
- Importing a machine learning model from a Caffe, Pytorch, TensorFlow, or other popular framework onto Vitis™ AI, and then optimizing and evaluating its effectiveness. Topics in this document that apply to this design process include:
- Embedded Software Development
- Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs. Topics in this document that apply to this design process include:
- Host Software Development
- Developing the application code, accelerator development, including library, XRT, and Graph API use. Topics in this document that apply to this design process include:
- Hardware, IP, and Platform Development
- Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:
- System Integration and Validation
- Integrating and validating the system functional performance, including timing, resource use, and power closure. Topics in this document that apply to this design process include: