AXI4-Lite Interface - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-04-12
Version
2.1 English

The DCMAC Subsystem provides a significant amount of internal statistics/status gathering and accumulation for up to six MAC channels as well as the six PHY ports. That internally stored information is accessible using the AXI4-Lite interface. For more details on the AXI4-Lite interface, see the AXI to APB Bridge LogiCORE IP Product Guide (PG073).

A complete description of the register map and the individual registers can be found in the Register Space section.