There are three primary output signal groups for data movement on the MAC I/F:
tx_macif_ts_id[5:0]indicates the time-slice/client ID currently active on the interface.
tx_macif_enaindicates that the cycle is valid.
tx_macif_data_<L>[65:0]contains the PCS data to be forwarded to the network, where <L> represents a data lane.
tx_macif_data interface consists of 24 separate lanes, each 66 bits
(one PCS block) wide. The sequence of channel IDs presented on the transmit data output
port directly correlates to the sequence of IDs presented on the channel request side of
the transmit MAC I/F. For example, if a request sequence of 39, 27, 30, 5, 6, 2 is
issued by the user logic, the receiving user logic can expect returning data with
tx_macif_ts_id sequence: 39, 27, 30, 5, 6, 2. The delay
between request and data is the sum of the DCMAC Subsystem request pipeline, the AXI user logic response time, and
then the DCMAC Subsystem transmit independent MAC
Although the ID sequence is guaranteed to be preserved, the request gaps
vld deasserted) might shift within the sequence. The ratio of
vld on the request interface is matched to the ratio of
ena on the data interface, but a deassertion of
vld at a particular point in the request calendar is not guaranteed
to be matched to a deassertion of
ena at the same point in the ID
sequence when data is returned.