Example Design Hierarchy - 2.1 English

Versal ACAP 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-04-12
Version
2.1 English

The following figure shows the DCMAC example design. In the block design, the DCMAC and GT Quad Base IP are connected along with the BUFG_GTs. For more information on the GT Quad Base IP, see the Versal ACAP Transceivers Wizard LogiCORE IP Product Guide (PG331).

Figure 1. DCMAC 600GE (6x100CAUI-4 / 6x100GAUI-4) with GTYP/GTM Example Design Block Diagram