The following shows timing diagram examples for the timer adjustments.
System Timer Overwrite
To overwrite the system timer, assert
D_ptp_st_overwrite_N and drive the desired 54-bit value onto the input
D_ptp_systemtimer_N. The overwrite is
triggered by toggling the signal
As mentioned earlier, if the
transition is sampled to the falling edge of the timer’s clock, a DDR phase
compensator automatically adds half a clock period (that is,
timer_increment / 2) to the system timer to help improve timer
Timer Frequency Set Coarse Adjustment
In this example, the
is set by providing a coarse adjustment to the
timer_increment (Method 2 on the Adjustment Interface).
ptp_st_adjustvalue is interpreted as being in units of 2-8 ns, which means it is mapped into the coarse portion of the
increment_value. The sub-nanosecond portion of the
increment_valueis set to
32’d0. To adjust the sub-nanosecond portion of the increment value, use the Timer Frequency Fine Adjust method.
Timer Frequency Fine Adjustment
Here is an example of fine-tuning the
system_timer frequency by adjusting the sub-nanosecond portion of the
increment value (Method 3 on the Adjustment Interface). The adjustment
is specified to be in units of 2-40 ns. The provided
signed adjustment value is added to the existing
increment_value and used moving forward.
In this diagram, a phase shift to the timer value is shown (Method 1 using the Adjustment Interface).
increment_valueonly changes for one
system_timeriteration (it is a one-shot adjustment) then returns to its previous value. The maximum allowable adjustment is a signed 18-bit value (two's complement) in units of 2-8 ns.